Daniel Carlsson

Daniel CarlssonGet to know Daniel:

I am a target oriented, curious and persevering engineer with a Master of Science in Applied Physics and Electrical Engineering – International Chineese with a master in System on Chip. I appreciate being challenged and solve problems to constantly contribute to changing, improving and develop both the product and myself.
My main interests and competences are in developing hardware and hardware near software and therefore I am happy to work in roles that require knowledge in both areas, like FPGA-development or designing ASICs. In my current assignment I have a role as a designer of a DSP processor written in Verilog, that also includes FPGA. In addition to this, I am also interested in more pure electronics design, as it also includes the same challenges as ASIC design, but I am happy to take on roles in firmware development or similar.

Operating systems/Platforms Microsoft Windows, Unix/Linux, Xilinx Spartan/Virtex, Embedded Linux
Programming/Scripting Verilog, SystemVerilog, Python (2.7 & 3.6) C/C++, VHDL, Bash, C#, LabView (CLAD), Matlab, SQL, SystemC
Tools Git, Synopsys VCS, Jenkins, Design Compiler, LabVIEW, Matlab, Cadence Virtuoso, MEntor Graphics Modelsim, HDL Designer, SPICE, Microsoft Office, Open Office, LaTex, CMake
Protocols APB, AXI, SPI, I2C, RS232, Wishbone
Skills/Experiences/Knowledge Agile development, Scrum, Kanban, Code review, Continuous Integration, Requirement rendering
Functional Safety ISO 26262, IEC 61508 (partly), Hazard and Operability Study, (HazOp), Fault Tree Analysis (FTA)
Previous Assignments
Assignment Description
FPGA developer

201804 – present

Development of accelerators on FPGA for image processing of images from camera in personal vehicle.

Xilinx Zynq SoC, Agile development, Functional Safety (ISO 26262), Sigasi Studio, VUnit, Xilinx Vivado, etc

Hardware Engineer

2014 – 201804

Development of a baseband processor and accompanying tool chain.

Development and expansion of baseband  processor in Verilog, mainly optimised for ASIC. FPGA development in Verilog. Development of test beds in SystemVerilog.

Development of test and tools in Python, Testing of processor in self developed test frameworks and unity tests for tools in nosetest and pytest.

Development of instruction set simulator for baseband processor in C++.

Embedded Systems Engineer

2012 – 2014

Performed a pre study and started development of a new version of an existing Active Noise Control system, for heavier vehicles.

Partook in research and work related to functional safety, mainly ISO 26262.